Wrapper/TAM Co-Optimization and constrained Test Scheduling for SOCs Using Rectangle Bin Packing

This paper describes an integrated framework for SOC test automation. This framework is based on a new approach for Wrapper/TAM co-optimization based on rectangle packing considering the diagonal length of the rectangles to emphasize on both TAM widths required by a core and its corresponding testing time .In this paper, an efficient algorithm has been proposed to construct wrappers that reduce testing time for cores. Rectangle packing has been used to develop an integrated scheduling algorithm that incorporates power constraints in the test schedule. The test power consumption is important to consider since exceeding the system’s power limit might damage the system. INTRODUCTION The development of microelectronic technology has lead to the implementation of system-on-chip (SOC), where a complete system, consisting of several application specific integrated circuit (ASIC), microprocessors, memories and other intellectual properties (IP) blocks, is implemented on a single chip. The increasing complexity of SOC has created many testing problems. The general problem of SOC test integration includes the design of TAM architectures, optimization of the core wrappers, and test scheduling. Test wrappers form the interface between cores and test access mechanisms (TAMs), while TAMs transport test data between SOC pins and test wrappers 3 . We address the problem of designing test wrappers and TAMs to minimize SOC testing time. While optimized wrappers reduce test application times for the individual cores, optimized TAMs lead to more efficient test data transport on-chip. Since wrappers influence TAM design, and vice versa, a co-optimization strategy is needed to jointly optimize the wrappers and the TAM for an SOC. In this paper, we propose a new approach to integrated wrapper/TAM co-optimization and test scheduling based on a general version of rectangle packing considering diagonal length of the rectangles to be packed. The main advantage of the proposed approach is that it minimizes the test application time while considering test power limitation. RELATED WORK Most prior research has either studied wrapper design and TAM optimization as independent problems, or not addressed the issue of sizing TAMs to minimize SOC testing time 1,3,13 .Alternative approaches that combine TAM design with test scheduling 5,15 do not address the problem of wrapper design and its relationship to TAM optimization. The first integrated method for Wrapper/TAM co-optimization was proposed in 10,11,12 . 10,12 are based on fixed-width TAMs which are inflexible and result in inefficient usage of TAM wires. An approach to wrapper/TAM co-optimization based on a generalized version of rectangle packing was proposed in 11 . This approach provides more flexible partitioning of the total TAM width among the cores. In a paper 16 , a method is proposed to address the test power consumption, where the test time for a system with wrapped cores is minimized while test power limitations are considered and tests are assigned to TAM wires. 6 address the SOC test scheduling problem by proposing a test scheduling technique that minimizes the test application time while considering test power consumption and test conflicts. PROPOSED WRAPPER DESIGN The purpose of our wrapper design algorithm (Fig. 1) is to construct a set of wrapper chains at each core. A wrapper chain includes a set of the scanned elements (scan-chains, wrapper input cells and wrapper output cells).The test time at a core is given by: Tcore = p × [1+max{si,so}] + min{si,so} where p is the number of test vectors to apply to the core and si (so) denotes the number of scan cycles required to load (unload) a test vector (test response) 10 . So, to reduce test time, we should minimize the longest wrapper chain (internal or external or both), i.e. max{si, so}. Recent research on wrapper design has stressed the need for balanced wrapper scan chains 3,10 to minimize the longest wrapper chain. Balanced wrapper scan chains are those that are as equal in length to each other as possible. The proposed Wrapper_Design algorithm tries to minimize core testing time as well as the TAM width required for the test wrapper. The objectives are achieved by balancing the lengths of the wrapper scan chains and imposing an upper bound on the total number of scanned elements. Our heuristic can be divided in two main parts; the first one for combinational cores and the second one for sequential cores. For combinational cores, there are two possibilities. If I+O (where I is the number of functional inputs and O the number of functional outputs) is below or equal to the TAM bandwidth limit, Wmax, then nothing is done and the number of connections to the TAM is I+O. If I+O is above Wmax, then some of the cells on the I/Os are chained together in order to reduce the number of needed connections to the TAM. For sequential cores, at first an upper bound is specified (Upper_Bound). The internal scan chains are then sorted in descending order. After that, each internal scan chain is successively assigned to the wrapper scan chain, whose length after this assignment is closest to, but not exceeding the length of the upper bound. In our algorithm, a new wrapper scan chain is created only when it is not possible to fit an internal scan chain into one of the existing wrapper scan chains without exceeding the length of the upper bound. At last, functional inputs and outputs are added to balance the wrapper scan chains. Results of wrapper design algorithm are given in Table 1. procedure Wrapper_Design (int Wmax, Core C) { //Wmax =TAM width ; //#SC=Total scan chain in Core C Total_Scan_Element= total I/O +∑ C.Scan_Chain_Length[i](1≤i<≤#SC); 1. If C.#SC=0 //combinational core If ( Total_Scan_Element <= Wmax ) Assign one bit on every I/O wrapper cell; Else Design Wmax wrapper scan chains; 2.Else //sequential core Mid_Lines = Wmax / 2; Upper_Bound = Total_Scan_Element /Mid_Lines ; Sort the internal scan chains in descending order of their length; For each scan chain SC For each wrapper scan chain W already created If ( Length(W)+Length(SC)<=Upper_Bound ) Assign the scan chain to this wrapper scanchain W ; Else Create a new Wrapper scan chain Wnew ; Assign the scan chain to this wrapper scanchain Wnew ; Add functional I/O to balance the wrapper chains; } Fig. 1 Algorithm for wrapper design TAM size TAM utilized (TAMu) Longest Scan chain 50-64 48-49 32-47 24-31 20-23 16-19 14-15 12-13 10-11 8-9 6-7 4-5 2-3 1 47 39 24 16 12 10 8 7 6 5 4 3 2 1 521 1021 1042 1563 2084 2605 3126 3647 4689 5729 7809 11969 23789 24278 Table 1. Result of Wrapper_Design for core 6 of p93791 4 TAM DESIGN AND TEST SCHEDULING The general integrated wrapper/TAM co-optimization and test scheduling problem that we address in this paper is as follows. We are given the total SOC TAM width and the test set parameters for each core. The set of parameters for each core includes the number of primary I/Os, test patterns, scan chains and scan chain lengths. The goal is to determine the TAM width and a wrapper design for each core, and a test schedule that minimizes the testing time for the SOC such that the following constraints are satisfied: 1. The total number of TAM wires utilized at any moment does not exceed Wmax; 2. The maximum power dissipation value is not exceeded. We formulate this problem as a progression of two problems of increasing complexity. These two problems are as follows: Problem 1: wrapper/TAM co-optimization and test Scheduling Problem 2: wrapper/TAM co-optimization and test scheduling with power constraints. In this section, we address Problem 1 and show how wrapper/TAM co-optimization can be integrated with test scheduling. In the next section, we show how this problem is generalized to include power constraintsProblem 2. Problem 1: determine the TAM width to be assigned and design a wrapper for each core and schedule the tests for the SOC in such a way that minimizes the total testing time as well as TAM width utilization and the total number of TAM wires utilized at any moment does not exceed total TAM width when a set of parameters for each core is given.. The concept of using rectangles for core test representation has been used before in 8,11,15 . Consider a SOC having N cores and let Ri be the set of rectangles for core i, 1 ≤ i ≤ N. Generalized version of rectangle packing problem Problem-RP1 is as follows: select a rectangle R from Ri for each set Ri, 1 ≤i ≤N and pack the selected rectangles in a bin of fixed height and unbounded width such that no two rectangle overlap and the width to which the bin is filled is minimized. Each rectangle selected is not allowed to be split vertically in our rectangle packing. Problem-RP1 can be shown to be Νρ -hard. A special case of Problem-RP1, in which the cardinality of each set Ri, 1≤i ≤N equals one, and no rectangles are allowed to be split, directly corresponds to the rectangle packing problem in 17 . Since the rectangle packing problem was shown to be Νρ -hard in 17 (by restriction to Bin Packing), Problem-RP1 is also Νρ -hard. Fig. 2 Example test schedule using rectangle packing We solve the Problem 1 by generalized version of rectangle packing or two-dimensional packing Problem-RP1 .We use the Wrapper_Design algorithm to obtain the different test times for each core for varying values of TAM width. A set of rectangles for a core can now be constructed, such that the height of each rectangle corresponds to a different TAM width and the width of the rectangle represents the core test application time for this value of TAM width. Problem-RP1 relates to problem 1 as follows; see Fig. 2.The height of the rectangle selected for a core corresponds to the TAM width assigned to the core, while the rectangle width corresponds to its testing time. The height of the bin corresponds to the total SOC TAM width, and the width to which the bin is ultimately filled corresponds to the system testing time that is to be minimized. The unfilled area of the bin corresponds to the idle time on TAM wires during test. Furthermore, the distance between the left edge of each rectangle and the left edge of the bin corresponds to the begin time of each core test. Our approach emphasizes on both testing time of a core and the TAM width required achieving that testing time by considering the diagonal length of rectangles. Diagonal length emphasizes on both testing time and TAM width since DL=√W + H where W, H, DL denotes width, height and diagonal length of the rectangles respectively. Consider three rectangles R[1] = {H=32, W=7.1, DL=32.78}, R[2] = {H=16, W=13.8,DL=21.13}, R[3] = {H=32, W=5.4,DL=32.45). Here if we take into account testing time(W), then we should pack R[2] first ,followed by R[1]and R[3] . But when we consider diagonal lengths, we pack R[1], R[3], R[2] in sequence, and get the result that is extremely efficient. Our approach minimizes TAM width utilization also by assigning TAMu wires to a core to achieve a specific testing time. For example, in our proposed Wrapper_Design , all TAM widths from 50 up to 64 result in the same testing time of 114317 cycles and same TAM width utilization(TAMu) of 47 for core 6 in p93791(Table 1).So, to achieve testing time of 114317 cycles TAMu value 47 is used in our proposed approach. POWER CONSTRAINED TEST SCHEULING This section, describes Problem 2(Integrated TAM design and power constrained test scheduling) in details and then formulates problem Problem-RP2, a generalized version of Problem-RP1 that is equivalent to Problem 2. Problem 2: solve Problem 1, such that: 1. The maximum power dissipation value Pmax is not exceeded. Power constraints must be incorporated in the schedule to ensure that the power rating of the SOC is not exceeded during test. Problem 2 can be expressed in terms of rectangle packing as follows: consider a SOC having N cores, and: 1. Let Ri be the set of rectangles for core i, 1 ≤ i ≤ N 2. Let tests for core i have a power dissipation of Pi. Problem-RP2: solve Problem-RP1 ensuring that at any moment of time the sum of the Pi values for the rectangles selected must not exceeded the maximum specified value Pmax. Algorithm Test_Scheduling (Wmax, Core C[1...NC]) { 1.For each core C[i] ,construct a set of rectangles taking TAMu as rectangle height and its corresponding testing time as rectangle width such that TAMu ≤ Wmax. 2. Find the smallest (Tmin) among the testing time corresponding to MAX_TAMu of all cores. 3. For each core C[i], divide the width T[i] of all rectangles constructed in line 1 with Tmin. 4. For each core C[i] ,calculate Diagonal Length DL[i] = √ ( (W[i]) + (T[i])) where W[i] denotes MAX_TAMu and T[i] denotes corresponding reduced testing time. 5. Sort the Cores in descending order of their diagonal length calculated in line 4 and keep in list INITIAL[NC]. 6. Next_Schedule_Time = current_Time = 0; Wavail = Wmax; // TAM available ; Idle_Flag=False; // peak_tam[c] is equal to MAX_TAMu of core c ; // PENDING is a queue. 7. While (INITIAL and PENDING not Empty) { 8 If (Wavail > 0 and Idle_Flag=False)